Version 4.1
SHEET 1 2772 940
WIRE 928 -112 720 -112
WIRE 720 -96 720 -112
WIRE 720 -96 656 -96
WIRE 656 -48 656 -96
WIRE 720 -48 720 -96
WIRE 144 32 -32 32
WIRE 144 64 144 32
WIRE 656 64 656 16
WIRE 720 64 720 32
WIRE 720 64 656 64
WIRE -32 80 -32 32
WIRE 720 96 720 64
WIRE 928 128 928 -112
WIRE 144 176 144 144
WIRE 672 176 144 176
WIRE 144 208 144 176
WIRE -32 272 -32 160
WIRE 16 272 -32 272
WIRE 16 320 16 272
WIRE 16 320 -32 320
WIRE 144 320 144 288
WIRE 144 320 16 320
WIRE 720 320 720 192
WIRE 720 320 144 320
WIRE 928 320 928 208
WIRE 928 320 720 320
FLAG -32 320 0
SYMBOL voltage -32 64 R0
WINDOW 3 24 44 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 1.6e-6 1.6e-6 0.000016 0.000032 10)
SYMBOL nmos 672 96 R0
SYMATTR InstName M1
SYMATTR Value DMG1012T
SYMATTR Prefix X
SYMBOL res 704 -64 R0
SYMATTR InstName R3
SYMATTR Value 50
SYMBOL voltage 928 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL res 128 192 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 128 48 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL diode 672 16 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
TEXT -24 0 Left 2 ;Voltage Divider
TEXT -64 344 Left 2 !.tran 0 0.0003 0 0.0000001
TEXT 1400 -168 Left 2 !* DIODES INCORPORATED AND ITS AFFILIATED COMPANIES AND SUBSIDIARIES (COLLECTIVELY, "DIODES") \n* PROVIDE THESE SPICE MODELS AND DATA (COLLECTIVELY, THE "SM DATA") "AS IS" AND WITHOUT ANY \n* REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, INCLUDING ANY WARRANTY OF MERCHANTABILITY \n* OR FITNESS FOR A PARTICULAR PURPOSE, ANY WARRANTY ARISING FROM COURSE OF DEALING OR COURSE OF \n* PERFORMANCE, OR ANY WARRANTY THAT ACCESS TO OR OPERATION OF THE SM DATA WILL BE UNINTERRUPTED, \n* OR THAT THE SM DATA OR ANY SIMULATION USING THE SM DATA WILL BE ERROR FREE. TO THE MAXIMUM \n* EXTENT PERMITTED BY LAW, IN NO EVENT WILL DIODES BE LIABLE FOR ANY DIRECT OR INDIRECT, \n* SPECIAL, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH \n* THE PRODUCTION OR USE OF SM DATA, HOWEVER CAUSED AND UNDER WHATEVER CAUSE OF ACTION OR THEORY \n* OF LIABILITY BROUGHT (INCLUDING, WITHOUT LIMITATION, UNDER ANY CONTRACT, NEGLIGENCE OR OTHER \n* TORT THEORY OF LIABILITY), EVEN IF DIODES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, \n* AND DIODES' TOTAL LIABILITY (WHETHER IN CONTRACT, TORT OR OTHERWISE) WITH REGARD TO THE SM \n* DATA WILL NOT, IN THE AGGREGATE, EXCEED ANY SUMS PAID BY YOU TO DIODES FOR THE SM DATA.\n \n \n \n*SYM=POWMOSN\n.SUBCKT DMG1012T   10 20 30\n*     TERMINALS:  D  G  S\nM1   1  20  3  3  NMOS L=0.6U W=47.66m\nRD  10  1  220m\nRS  30  3  80m\nCGS  20  3  57p\nEGD 12  0  20  1  1\nVFB 14  0  0\nFFB  20  1  VFB  1\nCGD 13 14  27p\nR1  13  0  1.00\nD1  12 13  DLIM\nDDG 15 14  DCGD\nR2  12 15  1.00\nD2  15  0  DLIM\nDSD  3 10  DSUB\n.MODEL NMOS NMOS LEVEL=3 U0=500 VMAX=80k\n+ ETA=0.1m VTO=0.99 TOX=16.8n NSUB=4.57e16\n.MODEL DCGD D CJO=27p VJ=80m M=0.320\n.MODEL DSUB D IS=36.1n N=1.50 RS=21.8m BV=20\n+ CJO=14p VJ=0.800 M=0.420\n.MODEL DLIM D IS=100U\n.ENDS